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Infotech Education Society Journal

of Science and Technology
                                                  ISSN 2455-4391
Volume 1 Issue 1

Paper Title
APPROCHES & TECHNIQUES FOR REDUCTION OF POWER DISSIPATION IN VLSI CIRCUIT
Author Name
Author Kamlesh Saha
Year of Publication
2016
Volume and Issue
Volume 1 Issue 2
Abstract  
In this technical era Low Power VLSI Design is part and parcel thing for electronics industries. Power dissipation plays an important role for VLSI chip design. Low power VLSI design technology reducing power consumption and over all power management on chip are the key challenges below 100nm due to increased complexity. For many designs, optimization of power is important as timing due to the need to reduce complexity and extended reliability. For power management leakage current also plays an important role in low power VLSI designs. Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. This paper describes about the various approaches and techniques for low power VLSI design. By the aid of these techniques we can design future intelligence circuit which is based on low power chip design.
PaperID
2016/01/IESJST/2/1
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